1. Field of the Invention
This invention relates to circuits and methods for transferring signals across clock domains and particularly to input and output cells for a processor having a core that operates at a frequency that is a half-integer multiple of a bus clock frequency.
2. Description of Related Art
Microprocessors commonly employ a system bus that operates at a fixed clock frequency according to an established protocol and a processing core that operates at a higher frequency selected according to circuit performance. For example, a 66 MHz bus clock frequency is currently common for microprocessors that have processing cores operating at 133 MHz, 166 MHz, 200 MHz and 233 MHz. For such microprocessors, bus signals such as control, data, and address signals that are transmitted to or from the processor are synchronized with the bus clock. Conventionally, such bus signals become valid somewhat before an edge (conventionally a rising edge) of the bus clock signal and remain valid after the edge of the bus clock signal. The time between asserting a valid bus signal and the bus clock signal edge is referred to as the set-up time of the signal. The time during which the signal is valid after the edge of the bus clock signal is referred to as the hold time. The bus protocol defines required set-up and hold times for variety of types of bus signals.
In the processor, most bus signals must be resynchronized with a processor clock for the processing core. To resynchronize an input signal, a circuit element operated off the processor clock latches a signal from a circuit element operated off the bus clock. This is sometimes referred to as the signal crossing from the clock domain of the bus to the clock domain of the processing core. Similarly, a circuit element operated off the bus clock latches signals from the processing core to resynchronize the signals with the bus clock for output to the bus. Input/output (I/O) cells for a processor commonly synchronize signals crossing between a clock domain operating at the bus clock frequency and the clock domain of the processing core.
The processor clock is typically generated from the bus clock but is only approximately synchronized with the bus clock because frequency multipliers, phase locked loops, and other circuits that generate or distribute the processor clock signal are subject to skew. Such skew creates a range of possible time separations between edges of the bus clock signal and edges of the processor clock signal. The skew can be a problem when a bus protocol provides short set-up and hold times for bus signals because the time during which a signal is valid may not sufficiently overlap the time required for latching the signal when the signal crosses between time domains. Another concern when passing signals between the clock domains arises when the processor clock frequency is a non-integer multiple of the bus clock frequency. Bus signals are commonly synchronized with the rising edges of the bus clock signal, but when the processor clock frequency is a non-integer multiple of the bus clock frequency, the rising edge of the processor clock signal that is closest in time to a rising edge of the bus clock signal may be significantly offset. For example, if the processor clock frequency is an odd multiple of half of the bus clock frequency, half of the rising edges of the bus clock signal are approximately synchronized with falling edges of the processor clock signal and offset from a nearest rising edge of the processor clock signal by about half the period of the processor clock. Accordingly, a bus signal that is synchronized with a rising edge of the bus clock signal commonly does not have enough set-up or hold time for latching at the next rising edge of the processor clock signal.
Input/output cells for processors are sought that can accommodate a processor clock that has a frequency that is a non-integer multiple of the bus clock and is skewed relative to the bus clock.